<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
<html xmlns="http://www.w3.org/1999/xhtml">
<head>
<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
<meta http-equiv="X-UA-Compatible" content="IE=9"/>
<meta name="generator" content="Doxygen 1.8.5"/>
<title>mipi_rx_phy: xmipi_rx_phy_hw.h File Reference</title>
<link href="tabs.css" rel="stylesheet" type="text/css"/>
<script type="text/javascript" src="jquery.js"></script>
<script type="text/javascript" src="dynsections.js"></script>
<link href="navtree.css" rel="stylesheet" type="text/css"/>
<script type="text/javascript" src="resize.js"></script>
<script type="text/javascript" src="navtree.js"></script>
<script type="text/javascript">
  $(document).ready(initResizable);
  $(window).load(resizeHeight);
</script>
<link href="doxygen.css" rel="stylesheet" type="text/css" />
<link href="HTML_custom.css" rel="stylesheet" type="text/css"/>
</head>
<body>
<div id="top"><!-- do not remove this div, it is closed by doxygen! -->
<div id="titlearea">
<table cellspacing="0" cellpadding="0">
 <tbody>
 <tr style="height: 56px;">
  <td id="projectlogo"><img alt="Logo" src="xlogo_bg.png"/></td>
  <td style="padding-left: 0.5em;">
   <div id="projectname">mipi_rx_phy
   </div>
   <div id="projectbrief">Vitis Drivers API Documentation</div>
  </td>
 </tr>
 </tbody>
</table>
</div>
<!-- end header part -->
<!-- Generated by Doxygen 1.8.5 -->
  <div id="navrow1" class="tabs">
    <ul class="tablist">
      <li><a href="index.html"><span>Overview</span></a></li>
      <li><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
      <li><a href="globals.html"><span>APIs</span></a></li>
      <li><a href="files.html"><span>File&#160;List</span></a></li>
      <li><a href="pages.html"><span>Examples</span></a></li>
    </ul>
  </div>
</div><!-- top -->
<div id="side-nav" class="ui-resizable side-nav-resizable">
  <div id="nav-tree">
    <div id="nav-tree-contents">
      <div id="nav-sync" class="sync"></div>
    </div>
  </div>
  <div id="splitbar" style="-moz-user-select:none;" 
       class="ui-resizable-handle">
  </div>
</div>
<script type="text/javascript">
$(document).ready(function(){initNavTree('xmipi__rx__phy__hw_8h.html','');});
</script>
<div id="doc-content">
<div class="header">
  <div class="summary">
<a href="#define-members">Macros</a>  </div>
  <div class="headertitle">
<div class="title">xmipi_rx_phy_hw.h File Reference</div>  </div>
</div><!--header-->
<div class="contents">
<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
Macros</h2></td></tr>
<tr class="memitem:ga10de00dc29c09ca2f4cd07b791947303"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#ga10de00dc29c09ca2f4cd07b791947303">XMIPI_RX_PHY_HW_H_</a></td></tr>
<tr class="memdesc:ga10de00dc29c09ca2f4cd07b791947303"><td class="mdescLeft">&#160;</td><td class="mdescRight">Prevent circular inclusions by using protection macros.  <a href="group__mipi__rx__phy.html#ga10de00dc29c09ca2f4cd07b791947303">More...</a><br/></td></tr>
<tr class="separator:ga10de00dc29c09ca2f4cd07b791947303"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Device registers</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>Register sets of MIPI_RX_PHY </p>
</div></td></tr>
<tr class="memitem:ga0bf404750dfcaaefdd04d672d4a34ed2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#ga0bf404750dfcaaefdd04d672d4a34ed2">XMIPI_RX_PHY_CTRL_REG_OFFSET</a>&#160;&#160;&#160;0x00000000</td></tr>
<tr class="memdesc:ga0bf404750dfcaaefdd04d672d4a34ed2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Control Register.  <a href="group__mipi__rx__phy.html#ga0bf404750dfcaaefdd04d672d4a34ed2">More...</a><br/></td></tr>
<tr class="separator:ga0bf404750dfcaaefdd04d672d4a34ed2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf427e80f588294f6bd021db121fc76fd"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#gaf427e80f588294f6bd021db121fc76fd">XMIPI_RX_PHY_VERSION_REG_OFFSET</a>&#160;&#160;&#160;0x00000004</td></tr>
<tr class="memdesc:gaf427e80f588294f6bd021db121fc76fd"><td class="mdescLeft">&#160;</td><td class="mdescRight">Core Version Register.  <a href="group__mipi__rx__phy.html#gaf427e80f588294f6bd021db121fc76fd">More...</a><br/></td></tr>
<tr class="separator:gaf427e80f588294f6bd021db121fc76fd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5d73b98adf4b04216bb1742cc3ad92d6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#ga5d73b98adf4b04216bb1742cc3ad92d6">XMIPI_RX_PHY_INIT_TIMER_REG_OFFSET</a>&#160;&#160;&#160;0x00000008</td></tr>
<tr class="memdesc:ga5d73b98adf4b04216bb1742cc3ad92d6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Initialization Timer Register.  <a href="group__mipi__rx__phy.html#ga5d73b98adf4b04216bb1742cc3ad92d6">More...</a><br/></td></tr>
<tr class="separator:ga5d73b98adf4b04216bb1742cc3ad92d6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gace1a808a2597c0a1395016ec4de67d8a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#gace1a808a2597c0a1395016ec4de67d8a">XMIPI_RX_PHY_HSTIMEOUT_REG_OFFSET</a>&#160;&#160;&#160;0x00000010</td></tr>
<tr class="memdesc:gace1a808a2597c0a1395016ec4de67d8a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Watchdog timeout in HS mode Register.  <a href="group__mipi__rx__phy.html#gace1a808a2597c0a1395016ec4de67d8a">More...</a><br/></td></tr>
<tr class="separator:gace1a808a2597c0a1395016ec4de67d8a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1f2a7ab905af5a63575745e79fa1afef"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#ga1f2a7ab905af5a63575745e79fa1afef">XMIPI_RX_PHY_ESCTIMEOUT_REG_OFFSET</a>&#160;&#160;&#160;0x00000014</td></tr>
<tr class="memdesc:ga1f2a7ab905af5a63575745e79fa1afef"><td class="mdescLeft">&#160;</td><td class="mdescRight">Goto Stop state on timeout timer Register.  <a href="group__mipi__rx__phy.html#ga1f2a7ab905af5a63575745e79fa1afef">More...</a><br/></td></tr>
<tr class="separator:ga1f2a7ab905af5a63575745e79fa1afef"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6df3cddb2f8c6136193423656e1f8e54"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#ga6df3cddb2f8c6136193423656e1f8e54">XMIPI_RX_PHY_CLSTATUS_REG_OFFSET</a>&#160;&#160;&#160;0x00000018</td></tr>
<tr class="memdesc:ga6df3cddb2f8c6136193423656e1f8e54"><td class="mdescLeft">&#160;</td><td class="mdescRight">Clk lane PHY error Status Register.  <a href="group__mipi__rx__phy.html#ga6df3cddb2f8c6136193423656e1f8e54">More...</a><br/></td></tr>
<tr class="separator:ga6df3cddb2f8c6136193423656e1f8e54"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7ca8cc7e96c85d80a747864154b5ffa0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#ga7ca8cc7e96c85d80a747864154b5ffa0">XMIPI_RX_PHY_DL0STATUS_REG_OFFSET</a>&#160;&#160;&#160;0x0000001C</td></tr>
<tr class="memdesc:ga7ca8cc7e96c85d80a747864154b5ffa0"><td class="mdescLeft">&#160;</td><td class="mdescRight">Data lane 0 PHY error Status Register.  <a href="group__mipi__rx__phy.html#ga7ca8cc7e96c85d80a747864154b5ffa0">More...</a><br/></td></tr>
<tr class="separator:ga7ca8cc7e96c85d80a747864154b5ffa0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4d6de41a345ab9b0da5a07936f3a5d8a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#ga4d6de41a345ab9b0da5a07936f3a5d8a">XMIPI_RX_PHY_DL1STATUS_REG_OFFSET</a>&#160;&#160;&#160;0x00000020</td></tr>
<tr class="memdesc:ga4d6de41a345ab9b0da5a07936f3a5d8a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Data lane 1 PHY error Status Register.  <a href="group__mipi__rx__phy.html#ga4d6de41a345ab9b0da5a07936f3a5d8a">More...</a><br/></td></tr>
<tr class="separator:ga4d6de41a345ab9b0da5a07936f3a5d8a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa7867d266b24387c2a89bb4c8e61306b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#gaa7867d266b24387c2a89bb4c8e61306b">XMIPI_RX_PHY_DL2STATUS_REG_OFFSET</a>&#160;&#160;&#160;0x00000024</td></tr>
<tr class="memdesc:gaa7867d266b24387c2a89bb4c8e61306b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Data lane 2 PHY error Status Register.  <a href="group__mipi__rx__phy.html#gaa7867d266b24387c2a89bb4c8e61306b">More...</a><br/></td></tr>
<tr class="separator:gaa7867d266b24387c2a89bb4c8e61306b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae602e9d94b72de6818a5b3f9e5b2bc82"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#gae602e9d94b72de6818a5b3f9e5b2bc82">XMIPI_RX_PHY_DL3STATUS_REG_OFFSET</a>&#160;&#160;&#160;0x00000028</td></tr>
<tr class="memdesc:gae602e9d94b72de6818a5b3f9e5b2bc82"><td class="mdescLeft">&#160;</td><td class="mdescRight">Data lane 3 PHY error Status Register.  <a href="group__mipi__rx__phy.html#gae602e9d94b72de6818a5b3f9e5b2bc82">More...</a><br/></td></tr>
<tr class="separator:gae602e9d94b72de6818a5b3f9e5b2bc82"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga941337f26bc908ba365194c7d1e152ab"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#ga941337f26bc908ba365194c7d1e152ab">XMIPI_RX_PHY_HSSETTLE0_REG_OFFSET</a>&#160;&#160;&#160;0x00000030</td></tr>
<tr class="memdesc:ga941337f26bc908ba365194c7d1e152ab"><td class="mdescLeft">&#160;</td><td class="mdescRight">HS Settle Register L0.  <a href="group__mipi__rx__phy.html#ga941337f26bc908ba365194c7d1e152ab">More...</a><br/></td></tr>
<tr class="separator:ga941337f26bc908ba365194c7d1e152ab"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga811dbc44fe9d3b4dc258652de27d661c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#ga811dbc44fe9d3b4dc258652de27d661c">XMIPI_RX_PHY_HSSETTLE1_REG_OFFSET</a>&#160;&#160;&#160;0x00000048</td></tr>
<tr class="memdesc:ga811dbc44fe9d3b4dc258652de27d661c"><td class="mdescLeft">&#160;</td><td class="mdescRight">HS Settle Register L1.  <a href="group__mipi__rx__phy.html#ga811dbc44fe9d3b4dc258652de27d661c">More...</a><br/></td></tr>
<tr class="separator:ga811dbc44fe9d3b4dc258652de27d661c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6c837a9e2b95486169ad376478bfc14e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#ga6c837a9e2b95486169ad376478bfc14e">XMIPI_RX_PHY_HSSETTLE2_REG_OFFSET</a>&#160;&#160;&#160;0x0000004C</td></tr>
<tr class="memdesc:ga6c837a9e2b95486169ad376478bfc14e"><td class="mdescLeft">&#160;</td><td class="mdescRight">HS Settle Register L2.  <a href="group__mipi__rx__phy.html#ga6c837a9e2b95486169ad376478bfc14e">More...</a><br/></td></tr>
<tr class="separator:ga6c837a9e2b95486169ad376478bfc14e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga832f2a3a308197b899ba0f7d0b33e908"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#ga832f2a3a308197b899ba0f7d0b33e908">XMIPI_RX_PHY_HSSETTLE3_REG_OFFSET</a>&#160;&#160;&#160;0x00000050</td></tr>
<tr class="memdesc:ga832f2a3a308197b899ba0f7d0b33e908"><td class="mdescLeft">&#160;</td><td class="mdescRight">HS Settle Register L3.  <a href="group__mipi__rx__phy.html#ga832f2a3a308197b899ba0f7d0b33e908">More...</a><br/></td></tr>
<tr class="separator:ga832f2a3a308197b899ba0f7d0b33e908"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Bitmasks and offsets of XMIPI_RX_PHY_CTRL_REG_OFFSET register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register is used for the enabling/disabling and resetting the MIPI_RX_PHY </p>
</div></td></tr>
<tr class="memitem:ga99a08282c67427601f56d2ad64234ed6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#ga99a08282c67427601f56d2ad64234ed6">XMIPI_RX_PHY_CTRL_REG_SOFTRESET_MASK</a>&#160;&#160;&#160;0x00000001</td></tr>
<tr class="memdesc:ga99a08282c67427601f56d2ad64234ed6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Soft Reset.  <a href="group__mipi__rx__phy.html#ga99a08282c67427601f56d2ad64234ed6">More...</a><br/></td></tr>
<tr class="separator:ga99a08282c67427601f56d2ad64234ed6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaec198293afc07be517b0ae8f92837d2c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#gaec198293afc07be517b0ae8f92837d2c">XMIPI_RX_PHY_CTRL_REG_PHYEN_MASK</a>&#160;&#160;&#160;0x00000002</td></tr>
<tr class="memdesc:gaec198293afc07be517b0ae8f92837d2c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable/Disable controller.  <a href="group__mipi__rx__phy.html#gaec198293afc07be517b0ae8f92837d2c">More...</a><br/></td></tr>
<tr class="separator:gaec198293afc07be517b0ae8f92837d2c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad2a85cb1a79f05bcfe068d2a5bb03233"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#gad2a85cb1a79f05bcfe068d2a5bb03233">XMIPI_RX_PHY_CTRL_REG_SOFTRESET_OFFSET</a>&#160;&#160;&#160;0</td></tr>
<tr class="memdesc:gad2a85cb1a79f05bcfe068d2a5bb03233"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit offset for Soft Reset.  <a href="group__mipi__rx__phy.html#gad2a85cb1a79f05bcfe068d2a5bb03233">More...</a><br/></td></tr>
<tr class="separator:gad2a85cb1a79f05bcfe068d2a5bb03233"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaceeabb8c562fc7a8eedf90bbdd63b4c5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#gaceeabb8c562fc7a8eedf90bbdd63b4c5">XMIPI_RX_PHY_CTRL_REG_PHYEN_OFFSET</a>&#160;&#160;&#160;1</td></tr>
<tr class="memdesc:gaceeabb8c562fc7a8eedf90bbdd63b4c5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit offset for PHY Enable.  <a href="group__mipi__rx__phy.html#gaceeabb8c562fc7a8eedf90bbdd63b4c5">More...</a><br/></td></tr>
<tr class="separator:gaceeabb8c562fc7a8eedf90bbdd63b4c5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Bitmasks and offsets of XMIPI_RX_PHY_INIT_REG_OFFSET register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register is used for lane Initialization.</p>
<p>Recommended to use 1ms or longer in for TX mode and 200us-500us for RX mode </p>
</div></td></tr>
<tr class="memitem:gab750cb7ee4477ebf02dee74a7e912949"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#gab750cb7ee4477ebf02dee74a7e912949">XMIPI_RX_PHY_INIT_REG_VAL_MASK</a>&#160;&#160;&#160;0xFFFFFFFF</td></tr>
<tr class="memdesc:gab750cb7ee4477ebf02dee74a7e912949"><td class="mdescLeft">&#160;</td><td class="mdescRight">Init Timer value in ns.  <a href="group__mipi__rx__phy.html#gab750cb7ee4477ebf02dee74a7e912949">More...</a><br/></td></tr>
<tr class="separator:gab750cb7ee4477ebf02dee74a7e912949"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga02c8e40953545ada2100d4431ffe3061"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#ga02c8e40953545ada2100d4431ffe3061">XMIPI_RX_PHY_INIT_REG_VAL_OFFSET</a>&#160;&#160;&#160;0</td></tr>
<tr class="memdesc:ga02c8e40953545ada2100d4431ffe3061"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit offset for Init Timer.  <a href="group__mipi__rx__phy.html#ga02c8e40953545ada2100d4431ffe3061">More...</a><br/></td></tr>
<tr class="separator:ga02c8e40953545ada2100d4431ffe3061"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Bitmask and offset of XMIPI_RX_PHY_HSTIMEOUT_REG_OFFSET register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register is used to program watchdog timer in high speed mode.</p>
<p>Default value is 65541. Valid range 1000-65541. </p>
</div></td></tr>
<tr class="memitem:ga2b315903c952abd8e09c802a1a6be4c3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#ga2b315903c952abd8e09c802a1a6be4c3">XMIPI_RX_PHY_HSTIMEOUT_REG_TIMEOUT_MASK</a>&#160;&#160;&#160;0xFFFFFFFF</td></tr>
<tr class="memdesc:ga2b315903c952abd8e09c802a1a6be4c3"><td class="mdescLeft">&#160;</td><td class="mdescRight">HS_RX_TIMEOUT Received.  <a href="group__mipi__rx__phy.html#ga2b315903c952abd8e09c802a1a6be4c3">More...</a><br/></td></tr>
<tr class="separator:ga2b315903c952abd8e09c802a1a6be4c3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gadec1619af7a2de87d591812729bc52d1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#gadec1619af7a2de87d591812729bc52d1">XMIPI_RX_PHY_HSTIMEOUT_REG_TIMEOUT_OFFSET</a>&#160;&#160;&#160;0</td></tr>
<tr class="memdesc:gadec1619af7a2de87d591812729bc52d1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit offset for Timeout.  <a href="group__mipi__rx__phy.html#gadec1619af7a2de87d591812729bc52d1">More...</a><br/></td></tr>
<tr class="separator:gadec1619af7a2de87d591812729bc52d1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Bitmask and offset of XMIPI_RX_PHY_ESCTIMEOUT_REG_OFFSET register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains Rx Data Lanes timeout for watchdog timer in escape mode. </p>
</div></td></tr>
<tr class="memitem:ga57f8374c40686716eb09f598db90d2d7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#ga57f8374c40686716eb09f598db90d2d7">XMIPI_RX_PHY_ESCTIMEOUT_REG_VAL_MASK</a>&#160;&#160;&#160;0xFFFFFFFF</td></tr>
<tr class="memdesc:ga57f8374c40686716eb09f598db90d2d7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Escape Timout Value.  <a href="group__mipi__rx__phy.html#ga57f8374c40686716eb09f598db90d2d7">More...</a><br/></td></tr>
<tr class="separator:ga57f8374c40686716eb09f598db90d2d7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga79f52cbaa7e2faa9b99f6c7f1c901d41"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#ga79f52cbaa7e2faa9b99f6c7f1c901d41">XMIPI_RX_PHY_ESCTIMEOUT_REG_VAL_OFFSET</a>&#160;&#160;&#160;0</td></tr>
<tr class="memdesc:ga79f52cbaa7e2faa9b99f6c7f1c901d41"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit offset for Escape Timeout.  <a href="group__mipi__rx__phy.html#ga79f52cbaa7e2faa9b99f6c7f1c901d41">More...</a><br/></td></tr>
<tr class="separator:ga79f52cbaa7e2faa9b99f6c7f1c901d41"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Bitmask and offset of XMIPI_RX_PHY_CLSTATUS_REG_OFFSET register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains the clock lane status and state machine control. </p>
</div></td></tr>
<tr class="memitem:ga39c1f0241f05d6c2dd4e6d86a952f1f4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#ga39c1f0241f05d6c2dd4e6d86a952f1f4">XMIPI_RX_PHY_CLSTATUS_REG_ERRCTRL_MASK</a>&#160;&#160;&#160;0x00000020</td></tr>
<tr class="memdesc:ga39c1f0241f05d6c2dd4e6d86a952f1f4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Clock lane control error.  <a href="group__mipi__rx__phy.html#ga39c1f0241f05d6c2dd4e6d86a952f1f4">More...</a><br/></td></tr>
<tr class="separator:ga39c1f0241f05d6c2dd4e6d86a952f1f4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8db6d7f19e0431ee20321b3a635a2eca"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#ga8db6d7f19e0431ee20321b3a635a2eca">XMIPI_RX_PHY_CLSTATUS_REG_STOPSTATE_MASK</a>&#160;&#160;&#160;0x00000010</td></tr>
<tr class="memdesc:ga8db6d7f19e0431ee20321b3a635a2eca"><td class="mdescLeft">&#160;</td><td class="mdescRight">Clock lane stop state.  <a href="group__mipi__rx__phy.html#ga8db6d7f19e0431ee20321b3a635a2eca">More...</a><br/></td></tr>
<tr class="separator:ga8db6d7f19e0431ee20321b3a635a2eca"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1004d17945d6005324cc685f1d7038ba"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#ga1004d17945d6005324cc685f1d7038ba">XMIPI_RX_PHY_CLSTATUS_REG_INITDONE_MASK</a>&#160;&#160;&#160;0x00000008</td></tr>
<tr class="memdesc:ga1004d17945d6005324cc685f1d7038ba"><td class="mdescLeft">&#160;</td><td class="mdescRight">Initialization done bit.  <a href="group__mipi__rx__phy.html#ga1004d17945d6005324cc685f1d7038ba">More...</a><br/></td></tr>
<tr class="separator:ga1004d17945d6005324cc685f1d7038ba"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac8c1a0b393d70ec50205cdff482db809"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#gac8c1a0b393d70ec50205cdff482db809">XMIPI_RX_PHY_CLSTATUS_REG_ULPS_MASK</a>&#160;&#160;&#160;0x00000004</td></tr>
<tr class="memdesc:gac8c1a0b393d70ec50205cdff482db809"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set in ULPS mode.  <a href="group__mipi__rx__phy.html#gac8c1a0b393d70ec50205cdff482db809">More...</a><br/></td></tr>
<tr class="separator:gac8c1a0b393d70ec50205cdff482db809"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0b072dcfbf16b94c76a98a422d609a8f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#ga0b072dcfbf16b94c76a98a422d609a8f">XMIPI_RX_PHY_CLSTATUS_REG_MODE_MASK</a>&#160;&#160;&#160;0x00000003</td></tr>
<tr class="memdesc:ga0b072dcfbf16b94c76a98a422d609a8f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Low, High, Esc mode.  <a href="group__mipi__rx__phy.html#ga0b072dcfbf16b94c76a98a422d609a8f">More...</a><br/></td></tr>
<tr class="separator:ga0b072dcfbf16b94c76a98a422d609a8f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga711f31fdbd2533e3ecaa03ec794cf127"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga711f31fdbd2533e3ecaa03ec794cf127"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XMIPI_RX_PHY_CLSTATUS_ALLMASK</b></td></tr>
<tr class="separator:ga711f31fdbd2533e3ecaa03ec794cf127"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gadbad3f46c30270a90ef31180b87631b8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#gadbad3f46c30270a90ef31180b87631b8">XMIPI_RX_PHY_CLSTATUS_REG_ERRCTRL_OFFSET</a>&#160;&#160;&#160;5</td></tr>
<tr class="memdesc:gadbad3f46c30270a90ef31180b87631b8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit offset for Control Error on Clock.  <a href="group__mipi__rx__phy.html#gadbad3f46c30270a90ef31180b87631b8">More...</a><br/></td></tr>
<tr class="separator:gadbad3f46c30270a90ef31180b87631b8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6590b147d777602a6a0196968c3c65bd"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#ga6590b147d777602a6a0196968c3c65bd">XMIPI_RX_PHY_CLSTATUS_REG_STOPSTATE_OFFSET</a>&#160;&#160;&#160;4</td></tr>
<tr class="memdesc:ga6590b147d777602a6a0196968c3c65bd"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit offset for Stop State on Clock.  <a href="group__mipi__rx__phy.html#ga6590b147d777602a6a0196968c3c65bd">More...</a><br/></td></tr>
<tr class="separator:ga6590b147d777602a6a0196968c3c65bd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8d24544680c66148c097358ce8b33727"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#ga8d24544680c66148c097358ce8b33727">XMIPI_RX_PHY_CLSTATUS_REG_INITDONE_OFFSET</a>&#160;&#160;&#160;3</td></tr>
<tr class="memdesc:ga8d24544680c66148c097358ce8b33727"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit offset for Initialization Done.  <a href="group__mipi__rx__phy.html#ga8d24544680c66148c097358ce8b33727">More...</a><br/></td></tr>
<tr class="separator:ga8d24544680c66148c097358ce8b33727"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga276f3c942ce84cd5cce3340f986845ee"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#ga276f3c942ce84cd5cce3340f986845ee">XMIPI_RX_PHY_CLSTATUS_REG_ULPS_OFFSET</a>&#160;&#160;&#160;2</td></tr>
<tr class="memdesc:ga276f3c942ce84cd5cce3340f986845ee"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit offset for ULPS.  <a href="group__mipi__rx__phy.html#ga276f3c942ce84cd5cce3340f986845ee">More...</a><br/></td></tr>
<tr class="separator:ga276f3c942ce84cd5cce3340f986845ee"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0e493b03e48ae8ded1acc92f89d19b83"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#ga0e493b03e48ae8ded1acc92f89d19b83">XMIPI_RX_PHY_CLSTATUS_REG_MODE_OFFSET</a>&#160;&#160;&#160;0</td></tr>
<tr class="memdesc:ga0e493b03e48ae8ded1acc92f89d19b83"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit offset for Mode bits.  <a href="group__mipi__rx__phy.html#ga0e493b03e48ae8ded1acc92f89d19b83">More...</a><br/></td></tr>
<tr class="separator:ga0e493b03e48ae8ded1acc92f89d19b83"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Bitmasks and offsets of XMIPI_RX_PHY_DLxSTATUS_REG_OFFSET register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains the data lanes status </p>
</div></td></tr>
<tr class="memitem:ga57c759b34a6fc44b9b6bc969d84b949f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#ga57c759b34a6fc44b9b6bc969d84b949f">XMIPI_RX_PHY_DLXSTATUS_REG_PACKETCOUNT_MASK</a>&#160;&#160;&#160;0xFFFF0000</td></tr>
<tr class="memdesc:ga57c759b34a6fc44b9b6bc969d84b949f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Packet Count.  <a href="group__mipi__rx__phy.html#ga57c759b34a6fc44b9b6bc969d84b949f">More...</a><br/></td></tr>
<tr class="separator:ga57c759b34a6fc44b9b6bc969d84b949f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae96674943b4c7ac2ef7f24e16d114f5e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#gae96674943b4c7ac2ef7f24e16d114f5e">XMIPI_RX_PHY_DLXSTATUS_REG_CALIB_STATUS_MASK</a>&#160;&#160;&#160;0x00000100</td></tr>
<tr class="memdesc:gae96674943b4c7ac2ef7f24e16d114f5e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Calib status.  <a href="group__mipi__rx__phy.html#gae96674943b4c7ac2ef7f24e16d114f5e">More...</a><br/></td></tr>
<tr class="separator:gae96674943b4c7ac2ef7f24e16d114f5e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae734cd3c1776660119a146b701d23039"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#gae734cd3c1776660119a146b701d23039">XMIPI_RX_PHY_DLXSTATUS_REG_CALIB_COMPLETE_MASK</a>&#160;&#160;&#160;0x00000080</td></tr>
<tr class="memdesc:gae734cd3c1776660119a146b701d23039"><td class="mdescLeft">&#160;</td><td class="mdescRight">Calib complete.  <a href="group__mipi__rx__phy.html#gae734cd3c1776660119a146b701d23039">More...</a><br/></td></tr>
<tr class="separator:gae734cd3c1776660119a146b701d23039"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9398f883326211edd06dc8d2c7bb1017"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#ga9398f883326211edd06dc8d2c7bb1017">XMIPI_RX_PHY_DLXSTATUS_REG_STOP_MASK</a>&#160;&#160;&#160;0x00000040</td></tr>
<tr class="memdesc:ga9398f883326211edd06dc8d2c7bb1017"><td class="mdescLeft">&#160;</td><td class="mdescRight">Stop State on data lane.  <a href="group__mipi__rx__phy.html#ga9398f883326211edd06dc8d2c7bb1017">More...</a><br/></td></tr>
<tr class="separator:ga9398f883326211edd06dc8d2c7bb1017"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga193d957c5131a06eb4edf387464e8b23"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#ga193d957c5131a06eb4edf387464e8b23">XMIPI_RX_PHY_DLXSTATUS_REG_ESCABRT_MASK</a>&#160;&#160;&#160;0x00000020</td></tr>
<tr class="memdesc:ga193d957c5131a06eb4edf387464e8b23"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set on Data Lane Esc timeout occurs.  <a href="group__mipi__rx__phy.html#ga193d957c5131a06eb4edf387464e8b23">More...</a><br/></td></tr>
<tr class="separator:ga193d957c5131a06eb4edf387464e8b23"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga80f071df87fac8194c77e2b17ca96f89"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#ga80f071df87fac8194c77e2b17ca96f89">XMIPI_RX_PHY_DLXSTATUS_REG_HSABRT_MASK</a>&#160;&#160;&#160;0x00000010</td></tr>
<tr class="memdesc:ga80f071df87fac8194c77e2b17ca96f89"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set on Data Lane HS timeout.  <a href="group__mipi__rx__phy.html#ga80f071df87fac8194c77e2b17ca96f89">More...</a><br/></td></tr>
<tr class="separator:ga80f071df87fac8194c77e2b17ca96f89"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga375d4e779b8a019e67f724697281698f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#ga375d4e779b8a019e67f724697281698f">XMIPI_RX_PHY_DLXSTATUS_REG_INITDONE_MASK</a>&#160;&#160;&#160;0x00000008</td></tr>
<tr class="memdesc:ga375d4e779b8a019e67f724697281698f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set after initialization.  <a href="group__mipi__rx__phy.html#ga375d4e779b8a019e67f724697281698f">More...</a><br/></td></tr>
<tr class="separator:ga375d4e779b8a019e67f724697281698f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga17bd1c2c7ce0df5dbd19c46e6ea3feb4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#ga17bd1c2c7ce0df5dbd19c46e6ea3feb4">XMIPI_RX_PHY_DLXSTATUS_REG_ULPS_MASK</a>&#160;&#160;&#160;0x00000004</td></tr>
<tr class="memdesc:ga17bd1c2c7ce0df5dbd19c46e6ea3feb4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set when MIPI_RX_PHY in ULPS mode.  <a href="group__mipi__rx__phy.html#ga17bd1c2c7ce0df5dbd19c46e6ea3feb4">More...</a><br/></td></tr>
<tr class="separator:ga17bd1c2c7ce0df5dbd19c46e6ea3feb4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8b20becb98cc3e299a6791e4a27165e5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#ga8b20becb98cc3e299a6791e4a27165e5">XMIPI_RX_PHY_DLXSTATUS_REG_MODE_MASK</a>&#160;&#160;&#160;0x00000003</td></tr>
<tr class="memdesc:ga8b20becb98cc3e299a6791e4a27165e5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Control Mode (Esc, Low, High) of Data Lane.  <a href="group__mipi__rx__phy.html#ga8b20becb98cc3e299a6791e4a27165e5">More...</a><br/></td></tr>
<tr class="separator:ga8b20becb98cc3e299a6791e4a27165e5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2cbc32ec0c5d7ba9dda469abcac52d47"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga2cbc32ec0c5d7ba9dda469abcac52d47"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XMIPI_RX_PHY_DLXSTATUS_ALLMASK</b></td></tr>
<tr class="separator:ga2cbc32ec0c5d7ba9dda469abcac52d47"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga998420b025e47070ad9a0d79ff4068b5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#ga998420b025e47070ad9a0d79ff4068b5">XMIPI_RX_PHY_DLXSTATUS_REG_PACKCOUNT_OFFSET</a>&#160;&#160;&#160;16</td></tr>
<tr class="memdesc:ga998420b025e47070ad9a0d79ff4068b5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit offset packet count.  <a href="group__mipi__rx__phy.html#ga998420b025e47070ad9a0d79ff4068b5">More...</a><br/></td></tr>
<tr class="separator:ga998420b025e47070ad9a0d79ff4068b5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8ab0be5e794c5b009c0fe65359589ac5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#ga8ab0be5e794c5b009c0fe65359589ac5">XMIPI_RX_PHY_DLXSTATUS_REG_CALIB_STATUS_OFFSET</a>&#160;&#160;&#160;8</td></tr>
<tr class="memdesc:ga8ab0be5e794c5b009c0fe65359589ac5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit offset calib status.  <a href="group__mipi__rx__phy.html#ga8ab0be5e794c5b009c0fe65359589ac5">More...</a><br/></td></tr>
<tr class="separator:ga8ab0be5e794c5b009c0fe65359589ac5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4096f64ca0e39e289b86235fca5a037c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#ga4096f64ca0e39e289b86235fca5a037c">XMIPI_RX_PHY_DLXSTATUS_REG_CALIB_COMPLETE_OFFSET</a>&#160;&#160;&#160;7</td></tr>
<tr class="memdesc:ga4096f64ca0e39e289b86235fca5a037c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit offset Calib complete.  <a href="group__mipi__rx__phy.html#ga4096f64ca0e39e289b86235fca5a037c">More...</a><br/></td></tr>
<tr class="separator:ga4096f64ca0e39e289b86235fca5a037c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8014b37b88e35bbf981445e019063b64"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#ga8014b37b88e35bbf981445e019063b64">XMIPI_RX_PHY_DLXSTATUS_REG_STOP_OFFSET</a>&#160;&#160;&#160;6</td></tr>
<tr class="memdesc:ga8014b37b88e35bbf981445e019063b64"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit offset for Stop State.  <a href="group__mipi__rx__phy.html#ga8014b37b88e35bbf981445e019063b64">More...</a><br/></td></tr>
<tr class="separator:ga8014b37b88e35bbf981445e019063b64"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7e3da7655adcb229ff3b0405df9fda81"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#ga7e3da7655adcb229ff3b0405df9fda81">XMIPI_RX_PHY_DLXSTATUS_REG_ESCABRT_OFFSET</a>&#160;&#160;&#160;5</td></tr>
<tr class="memdesc:ga7e3da7655adcb229ff3b0405df9fda81"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit offset for Escape Abort.  <a href="group__mipi__rx__phy.html#ga7e3da7655adcb229ff3b0405df9fda81">More...</a><br/></td></tr>
<tr class="separator:ga7e3da7655adcb229ff3b0405df9fda81"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga848eac0c720848135936180fe5565fcf"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#ga848eac0c720848135936180fe5565fcf">XMIPI_RX_PHY_DLXSTATUS_REG_HSABRT_OFFSET</a>&#160;&#160;&#160;4</td></tr>
<tr class="memdesc:ga848eac0c720848135936180fe5565fcf"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit offset for High Speed Abort.  <a href="group__mipi__rx__phy.html#ga848eac0c720848135936180fe5565fcf">More...</a><br/></td></tr>
<tr class="separator:ga848eac0c720848135936180fe5565fcf"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac7e2936c9950b54b267e8a974681012d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#gac7e2936c9950b54b267e8a974681012d">XMIPI_RX_PHY_DLXSTATUS_REG_INITDONE_OFFSET</a>&#160;&#160;&#160;3</td></tr>
<tr class="memdesc:gac7e2936c9950b54b267e8a974681012d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit offset for Initialization done.  <a href="group__mipi__rx__phy.html#gac7e2936c9950b54b267e8a974681012d">More...</a><br/></td></tr>
<tr class="separator:gac7e2936c9950b54b267e8a974681012d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gadd52dd222d3e9ddaae7418d3b5206a8e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#gadd52dd222d3e9ddaae7418d3b5206a8e">XMIPI_RX_PHY_DLXSTATUS_REG_ULPS_OFFSET</a>&#160;&#160;&#160;2</td></tr>
<tr class="memdesc:gadd52dd222d3e9ddaae7418d3b5206a8e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit offset for ULPS.  <a href="group__mipi__rx__phy.html#gadd52dd222d3e9ddaae7418d3b5206a8e">More...</a><br/></td></tr>
<tr class="separator:gadd52dd222d3e9ddaae7418d3b5206a8e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga87a5f3801d85fe11d33349fe98c350b8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#ga87a5f3801d85fe11d33349fe98c350b8">XMIPI_RX_PHY_DLXSTATUS_REG_MODE_OFFSET</a>&#160;&#160;&#160;0</td></tr>
<tr class="memdesc:ga87a5f3801d85fe11d33349fe98c350b8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit offset for Modes.  <a href="group__mipi__rx__phy.html#ga87a5f3801d85fe11d33349fe98c350b8">More...</a><br/></td></tr>
<tr class="separator:ga87a5f3801d85fe11d33349fe98c350b8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Bitmask and offset of XMIPI_RX_PHY_HSSETTLE_REG_OFFSET register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register is used to program the HS SETTLE register.</p>
<p>Default value is 135 + 10UI. </p>
</div></td></tr>
<tr class="memitem:gacd11b7eb937b614bc08120a16cc389ec"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#gacd11b7eb937b614bc08120a16cc389ec">XMIPI_RX_PHY_HSSETTLE_REG_TIMEOUT_MASK</a>&#160;&#160;&#160;0x1FF</td></tr>
<tr class="memdesc:gacd11b7eb937b614bc08120a16cc389ec"><td class="mdescLeft">&#160;</td><td class="mdescRight">HS_SETTLE value.  <a href="group__mipi__rx__phy.html#gacd11b7eb937b614bc08120a16cc389ec">More...</a><br/></td></tr>
<tr class="separator:gacd11b7eb937b614bc08120a16cc389ec"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gabf5dce54c9db1dc7b447fe302ef80e37"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#gabf5dce54c9db1dc7b447fe302ef80e37">XMIPI_RX_PHY_HSSETTLE_REG_TIMEOUT_OFFSET</a>&#160;&#160;&#160;0</td></tr>
<tr class="memdesc:gabf5dce54c9db1dc7b447fe302ef80e37"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit offset for HS_SETTLE.  <a href="group__mipi__rx__phy.html#gabf5dce54c9db1dc7b447fe302ef80e37">More...</a><br/></td></tr>
<tr class="separator:gabf5dce54c9db1dc7b447fe302ef80e37"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table>
</div><!-- contents -->
</div><!-- doc-content -->
<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
	<p class="footer">&copy; Copyright 2015-2022 Xilinx, Inc. All Rights Reserved.</p>
	<p class="footer">&copy; Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.</p>
</div>
</body>
</html>
